This invention relates to a process for forming an integrated circuit, and more particularly, to a process for forming fusible links in an integrated circuit.
As device generation goes beyond the 0.25 xcexcm rules, integrated circuits are transitioning from aluminum to copper metal interconnects. At the sane time, low dielectric constant (low k) materials have been proposed to replace silicon oxide as the primary material for dielectric insulation layers. Low k materials, which are typically polymers and have dielectric constant less than about 3.9 (the dielectric constant of silicon dioxide), reduce interconnect capacitance and crosstalk noise and enhance circuit performance. Some examples of low k dielectrics include polyimide, fluorocarbons, parylene, hydrogen silsequioxanes, and benzocyclobutenes. One method of fabricating integrated circuit using copper and low k dielectrics is a damascene process. In a damascene process, openings are provided in the low k dielectric layer that define the wiring patterns. The patterns are filled with a metallization metal using a filling technique. The metal may be planarized on the surface of the dielectric by removing excess metallization using a polishing method.
In integrated circuits having a large number of semiconductor devices fabricated on a silicon substrate, it is often necessary to provide conductors for connecting semiconductor devices with each other, as well as fusible links (fuses) that are coupled to conductors. The fuses may be opened (cut or blown) after fabrication. For example, in a memory circuit, fuses may be employed to replace defective memory arrays with redundant memory arrays. Fuses typical comprise metal links that can be explosively fused open by application of laser pulses or electrical pulses, which cause a portion of the link material to vaporize and/or melt. The integration of copper and low k dielectrics presents problems for the fabrication of integrated circuits having fusible links.
Accordingly, the present invention is directed to a process for forming a fusible link in an integrated circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an improved fusible link that can be integrated with the newer materials being used in semiconductor manufacturing, and a process for fabricating the same.
Additional features and advantages of the invention will be set forth in the descriptions that follow and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention provides a process for forming a fusible link in an integrated circuit, the process includes forming a final metal layer on a semiconductor substrate, wherein the substrate comprises devices fabricated from a copper metal layer and a low k dielectric material; patterning the final metal layer to form a fusible link that electrically connects the devices in the integrated circuit; forming a dielectric etch stop layer over the patterned final metal layer and the substrate; depositing a passivation layer over the dielectric etch stop layer over the fusible link; and removing the passivation layer over at least a portion of the fusible link and a surrounding area.
More specifically, the invention provides a process for forming a fusible link in an integrated circuit, the process comprising: (a) forming a second dielectric layer on a surface of an underlying metal interconnect layer and a first dielectric layer; (b) depositing an oxide layer at a thickness effective to prevent cracking of the oxide layer during a laser fuse process; (c) forming a via in the oxide layer and second dielectric layer extending to the underlying metal interconnect; (d) filling the via with a conductive material; (e) forming a final metal layer; (f) patterning the final metal layer to form a fusible link electrically connected to the via; (g) forming a dielectric etch stop layer over the patterned final metal layer and the oxide layer; (h) depositing a passivation layer over the dielectric etch stop layer; and (i) removing the passivation layer from above at least a portion of the fusible link and a surrounding area.
In another aspect, the present invention provides an article of manufacture comprising a semiconductor substrate having an integrated circuit formed thereon, the integrated circuit includes a fusible link formed according to the above process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.